1. Field of the Invention
The present invention relates to a method for evaluating a semiconductor device that has a MOS (Metal-Oxide-Semiconductor) structure, and particularly, relates to a method for evaluating a semiconductor device, which separates a gate leakage current by leakage path.
2. Description of the Related Art
Recently, a functional circuit using a semiconductor device has been actively developed. In order to realize a highly functional circuit, it is necessary to get a device to work at a high speed in order to realize a highly functional circuit, for which it is necessary that the device should be reduced in size and integrated. However, when a device becomes smaller, a decrease in threshold voltage or punch-through is caused to generate so-called short channel effect which means that a drain current cannot be controlled by a gate voltage. In order to suppress the short channel effect, it is effective to thin a gate insulating film. However, when the gate insulating film is thinned, a gate leakage current is increased to cause failure in operating a circuit.
On the other hand, according to Non-Patent Document 1 (Nicollian and Brews, MOS Physics and Technology, p. 378, FIG. 9.4), in the case of a MOS capacitor that has a small impurity concentration in a substrate, a depletion layer is extended transversely from an edge of a gate electrode. Since the width of an edge portion of the depletion layer is smaller as compared to that of the depletion layer just below the gate electrode, the edge portion of the depletion layer has a larger electric field as compared to the depletion layer just below the gate electrode. In consequence, a gate leakage current from the edge portion of the depletion layer is increased. Therefore, a gate leakage current generated in the MOS capacitor that has the small impurity concentration in the substrate includes an in-plane leakage current that flows from all over in a plane of the electrode and a leakage current from the edge portion of the depletion layer.
In addition, in the case of a field-effect semiconductor device such as a transistor, a leakage current is generated from an edge portion of a semiconductor in a source to drain direction (channel length direction). In this connection, top views of transistors, FIGS. 12A and 12C, and sectional views of the transistors, FIGS. 12B and 12D, are used to simply describe a leakage current from the aforementioned edge portion of the depletion layer and a leakage current from the edge portion of the semiconductor.
A depletion layer edge leakage current corresponds to a leakage current from an edge portion of a depletion layer, which is a current generated in a region surrounded by a dashed line in the top view of the transistor, FIG. 12A, and corresponds to a current that flows in a direction indicated by an arrow in the sectional view of the transistor, FIG. 12B. A silicon edge leakage current corresponds to a leakage current from the edge portion of the semiconductor in the source to drain direction (channel length direction), which is a current generated in a region surrounded by a dashed line in the top view of the transistor, FIG. 12C, and corresponds to a current that flows in a direction indicated by an arrow in the sectional view of the transistor, FIG. 12D. When an insulator is thinned, these regions become thinner as compared the other regions. Therefore, a high electric field is applied to generate a leakage current. The silicon edge leakage current depends on an etched shape of the semiconductor, and is a leakage current generated only in the field-effect transistor.